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tmp102 sbos397f ? august 2007 ? revised december 2015 tmp102 low-power digital temperature sensor with smbus and two-wire serial interface in sot563 1 features 3 description the tmp102 device is a digital temperature sensor 1 ? sot563 package (1.6-mm 1.6-mm) is a 68% ideal for ntc/ptc thermistor replacement where high smaller footprint than sot-23 accuracy is required. the device offers an accuracy ? accuracy without calibration: of 0.5 c without requiring calibration or external ? 2.0 c (max) from ? 25 c to 85 c component signal conditioning. device temperature sensors are highly linear and do not require complex ? 3.0 c (max) from ? 40 c to 125 c calculations or lookup tables to derive the ? low quiescent current: temperature. the on-chip 12-bit adc offers ? 10- a active (max) resolutions down to 0.0625 c. ? 1- a shutdown (max) the 1.6-mm 1.6-mm sot563 package is 68% ? supply range: 1.4 to 3.6 v smaller footprint than an sot-23 package. the tmp102 device features smbus ? , two-wire and i 2 c ? resolution: 12 bits interface compatibility, and allows up to four devices ? digital output: smbus ? , two-wire, and i 2 c on one bus. the device also features an smbus alert interface compatibility function. the device is specified to operate over ? nist traceable supply voltages from 1.4 to 3.6 v with the maximum quiescent current of 10 a over the full operating range. 2 applications the tmp102 device is ideal for extended temperature ? portable and battery-powered applications measurement in a variety of communication, ? power-supply temperature monitoring computer, consumer, environmental, industrial, and ? computer peripheral thermal protection instrumentation applications. the device is specified ? notebook computers for operation over a temperature range of ? 40 c to 125 c. ? battery management ? office machines the tmp102 production units are 100% tested against sensors that are nist-traceable and are ? thermostat controls verified with equipment that are nist-traceable ? electromechanical device temperatures through iso/iec 17025 accredited calibrations. ? general temperature measurements: device information (1) ? industrial controls part number package body size (nom) ? test equipment tmp102 sot563 (6) 1.60 mm 1.20 mm ? medical instrumentations (1) for all available packages, see the orderable addendum at the end of the data sheet. simplified schematic block diagram 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. diode temp. sensor ds a/d converter osc control logic serial interface config. and temp. register temperature scl 13 64 alert sda gnd 2 5 v+add0 scl gnd alert 2 4 1 add0 v+ 6 3 5 0.01 f two-wire host controller tmp102 1.4 v to 3.6 v sda pullup resistors supply bypass capacitor supply voltage 5 k productfolder sample &buy technical documents tools & software referencedesign support &community
tmp102 sbos397f ? august 2007 ? revised december 2015 www.ti.com table of contents 7.4 device functional modes ........................................ 13 1 features .................................................................. 1 7.5 programming ........................................................... 14 2 applications ........................................................... 1 8 application and implementation ........................ 20 3 description ............................................................. 1 8.1 application information ............................................ 20 4 revision history ..................................................... 2 8.2 typical application .................................................. 20 5 pin configuration and functions ......................... 3 9 power supply recommendations ...................... 22 6 specifications ......................................................... 3 10 layout ................................................................... 22 6.1 absolute maximum ratings ..................................... 3 10.1 layout guidelines ................................................. 22 6.2 handling ratings ....................................................... 3 10.2 layout example .................................................... 22 6.3 recommended operating conditions ....................... 4 11 device and documentation support ................. 23 6.4 thermal information .................................................. 4 11.1 documentation support ....................................... 23 6.5 electrical characteristics ........................................... 4 11.2 community resources .......................................... 23 6.6 timing requirements ............................................... 5 11.3 trademarks ........................................................... 23 6.7 typical characteristics .............................................. 6 11.4 electrostatic discharge caution ............................ 23 7 detailed description .............................................. 7 11.5 glossary ................................................................ 23 7.1 overview ................................................................... 7 12 mechanical, packaging, and orderable 7.2 functional block diagram ......................................... 7 information ........................................................... 23 7.3 feature description ................................................... 7 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision e (april 2015) to revision f page ? added ti design .................................................................................................................................................................... 1 ? added nist features bullet .................................................................................................................................................. 1 ? added last paragraph of description section ......................................................................................................................... 1 changes from revision d (december 2014) to revision e page ? changed the max value for the supply voltage from 3.6 to 4 in the absolute maximum ratings table ............................... 3 ? changed min, typ, and max values for the temperature accuracy (temperature error) parameter .................................. 4 ? changed the frequency from 2.85 to 3.4 mhz in the power supply section of the electrical characteristics table ....... 5 ? changed the temperature error vs temperature graph in the typical characteristics section ............................................ 6 ? changed the temperature error at 25 c graph in the typical characteristics section ......................................................... 6 changes from revision c (october 2012) to revision d page ? added handling rating table, feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section ............................................................... 3 ? changed parameters in timing requirements ...................................................................................................................... 5 changes from revision b (october 2008) to revision c page ? changed values for data hold time parameter in timing requirements .......................................................................... 11 2 submit documentation feedback copyright ? 2007 ? 2015, texas instruments incorporated product folder links: tmp102
tmp102 www.ti.com sbos397f ? august 2007 ? revised december 2015 5 pin configuration and functions drl package 6-pin sot563 top view pin functions pin i/o description no. name 1 scl i serial clock. open-drain output; requires a pullup resistor. 2 gnd ? ground 3 alert o overtemperature alert. open-drain output; requires a pullup resistor. 4 add0 i address select. connect to gnd or v+ 5 v+ i supply voltage, 1.4 v to 3.6 v 6 sda i/o serial data. open-drain output; requires a pullup resistor. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit supply voltage 4 v input voltage (2) ? 0.5 3.6 v output voltage 3.6 v operating temperature ? 55 150 c junction temperature 150 c storage temperature, t stg ? 60 150 c (1) stresses above these ratings may cause permanent damage. exposure to absolute maximum conditions for extended periods may degrade device reliability. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2) input voltage rating applies to all tmp102 input voltages. 6.2 handling ratings value unit human-body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v (esd) electrostatic discharge charged-device model (cdm), per jedec specification jesd22-c101 (2) 1000 v machine model (mm) 200 (1) level listed above is the passing level per ansi, esda, and jedec js-001. jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) level listed above is the passing level per eia-jedec jesd22-c101. jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. copyright ? 2007 ? 2015, texas instruments incorporated submit documentation feedback 3 product folder links: tmp102 12 3 65 4 sda v+ add0 scl gnd alert cbz
tmp102 sbos397f ? august 2007 ? revised december 2015 www.ti.com 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit v+ supply voltage 1.4 3.3 3.6 v t a operating free-air temperature ? 40 125 c 6.4 thermal information tmp102 thermal metric (1) drl (sot563) unit 6 pins r ja junction-to-ambient thermal resistance 200 c/w r jc(top) junction-to-case (top) thermal resistance 73.7 c/w r jb junction-to-board thermal resistance 34.4 c/w jt junction-to-top characterization parameter 3.1 c/w jb junction-to-board characterization parameter 34.2 c/w (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . 6.5 electrical characteristics at t a = 25 c and v s = 1.4 to 3.6 v, unless otherwise noted. parameter test conditions min typ max unit temperature input range ? 40 125 c ? 25 c to 85 c 0.5 2 accuracy (temperature error) c ? 40 c to 125 c 1 3 vs supply 0.2 0.5 c/v resolution 0.0625 c digital input/output input capacitance 3 pf v ih input logic high 0.7 (v+) 3.6 v v il input logic low ? 0.5 0.3 (v+) v i in input current 0 < v in < 3.6 v 1 a v+ > 2 v, i ol = 3 ma 0 0.4 sda v+ < 2 v, i ol = 3 ma 0 0.2 (v+) v ol output logic v v+ > 2 v, i ol = 3 ma 0 0.4 alert v+ < 2 v, i ol = 3 ma 0 0.2 (v+) resolution 12 bit conversion time 26 35 ms cr1 = 0, cr0 = 0 0.25 cr1 = 0, cr0 = 1 1 conversion modes conv/s cr1 = 1, cr0 = 0 (default) 4 cr1 = 1, cr0 = 1 8 timeout time 30 40 ms 4 submit documentation feedback copyright ? 2007 ? 2015, texas instruments incorporated product folder links: tmp102
tmp102 www.ti.com sbos397f ? august 2007 ? revised december 2015 electrical characteristics (continued) at t a = 25 c and v s = 1.4 to 3.6 v, unless otherwise noted. parameter test conditions min typ max unit power supply operating supply range +1.4 +3.6 v serial bus inactive, cr1 = 1, cr0 = 7 10 0 (default) serial bus active, scl frequency = i q average quiescent current 15 a 400 khz serial bus active, scl frequency = 85 3.4 mhz serial bus inactive 0.5 1 serial bus active, scl frequency = 10 i sd shutdown current 400 khz a serial bus active, scl frequency = 80 3.4 mhz temperature specified range ? 40 125 c operating range ? 55 150 c 6.6 timing requirements see the timing diagrams section for additional information. fast mode high-speed mode unit min typ max min typ max ? (scl) scl operating frequency v+ 0.001 0.4 0.001 2.85 mhz bus-free time between stop and t (buf) 600 160 ns start condition hold time after repeated start condition. t (hdsta) 600 160 ns after this period, the first clock is generated. see figure 7 t (susta) repeated start condition setup time 600 160 ns t (susto) stop condition setup time 600 160 ns t (hddat) data hold time 100 900 25 105 ns t (sudat) data setup time 100 25 ns t (low) scl-clock low period v+ , see figure 7 1300 210 ns t (high) scl-clock high period see figure 7 600 60 ns t fd data fall time see figure 7 300 80 ns see figure 7 300 ns t rd data rise time sclk 100 khz, 1000 ns see figure 7 t fc clock fall time see figure 7 300 40 ns t rc clock rise time see figure 7 300 40 ns copyright ? 2007 ? 2015, texas instruments incorporated submit documentation feedback 5 product folder links: tmp102
tmp102 sbos397f ? august 2007 ? revised december 2015 www.ti.com 6.7 typical characteristics at t a = 25 c and v+ = 3.3 v, unless otherwise noted. four conversions per second figure 1. average quiescent current vs temperature figure 2. shutdown current vs temperature figure 3. conversion time vs temperature figure 4. quiescent current vs bus frequency (temperature at 3.3-v supply) figure 6. temperature error at 25 c figure 5. temperature error vs temperature 6 submit documentation feedback copyright ? 2007 ? 2015, texas instruments incorporated product folder links: tmp102 temperature error ( q c) population -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0 10 20 30 40 50 60 70 d001 4038 36 34 32 30 28 26 24 22 20 temperature (c) -60 -20 40 60 140 160 conversion time (ms) 3.6 v supply 1.4 v supply -40 20 0 80 100 120 100 9080 70 60 50 40 30 20 10 0 bus frequency (hz) 1k 10k 100k 1m 10m i ( a) q 55 c +25 c +125 c 10 98 7 6 5 4 3 2 1 0 temperature (c) 60 40 0 40 140 160 i ( a) sd 3.6 v supply 1.4 v supply 20 20 60 80 100 120 2018 16 14 12 10 86 4 2 0 temperature (c) 60 20 40 60 140 160 i ( a) q 3.6 v supply 40 0 20 80 100 120 1.4 v supply temperature ( q c) temperature error ( q c) -60 -40 -20 0 20 40 60 80 100 120 140 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 d002 mean mean + 3 v mean 3 v
tmp102 www.ti.com sbos397f ? august 2007 ? revised december 2015 7 detailed description 7.1 overview the tmp102 device is a digital temperature sensor that is optimal for thermal-management and thermal- protection applications. the tmp102 device is two-wire, smbus and i 2 c interface-compatible. the device is specified over an operating temperature range of ? 40 c to 125 c. see functional block diagram for a block diagram of the tmp102 device. the temperature sensor in the tmp102 device is the chip itself. thermal paths run through the package leads as well as the plastic package. the package leads provide the primary thermal path because of the lower thermal resistance of the metal. an alternative version of the tmp102 device is available. the tmp112 device has highest accuracy, the same micro-package, and is pin-to-pin compatible. table 1. advantages of tmp112 versus tmp102 supply supply specified compatible supply local sensor accuracy device package voltage voltage resolution calibration interfaces current (max) (min) (max) drift slope sot563 12 bit 0.5 c: (0 c to 65 c) i 2 c tmp112 10 a 1.4 v 3.6 v yes 1.2 1.6 0.6 0.0625 c 1 c: (-40 c to 125 c) smbus sot563 12 bit 2 c: (25 c to 85 c) i 2 c tmp102 10 a 1.4 v 3.6 v no 1.2 1.6 0.6 0.0625 c 3 c: (-40 c to 125 c) smbus 7.2 functional block diagram 7.3 feature description 7.3.1 digital temperature output the digital output from each temperature measurement is stored in the read-only temperature register. the temperature register of the tmp102 device is configured as a 12-bit, read-only register (configuration register em bit = 0, see the extended mode (em) section), or as a 13-bit, read-only register (configuration register em bit = 1) that stores the output of the most recent conversion. two bytes must be read to obtain data and are listed in table 8 and table 9 . byte 1 is the most significant byte (msb), followed by byte 2, the least significant byte (lsb). the first 12 bits (13 bits in extended mode) are used to indicate temperature. the least significant byte does not have to be read if that information is not needed. the data format for temperature is summarized in table 2 and table 3 . one lsb equals 0.0625 c. negative numbers are represented in binary twos-complement format. following power-up or reset, the temperature register reads 0 c until the first conversion is complete. bit d0 of byte 2 indicates normal mode (em bit = 0) or extended mode (em bit = 1) , and can be used to distinguish between the two temperature register data formats. the unused bits in the temperature register always read 0. copyright ? 2007 ? 2015, texas instruments incorporated submit documentation feedback 7 product folder links: tmp102 diode temp. sensor ds a/d converter osc control logic serial interface config. and temp. register temperature scl 13 64 alert sda gnd 2 5 v+add0
tmp102 sbos397f ? august 2007 ? revised december 2015 www.ti.com feature description (continued) table 2. 12-bit temperature data format (1) temperature ( c) digital output (binary) hex 128 0111 1111 1111 7ff 127.9375 0111 1111 1111 7ff 100 0110 0100 0000 640 80 0101 0000 0000 500 75 0100 1011 0000 4b0 50 0011 0010 0000 320 25 0001 1001 0000 190 0.25 0000 0000 0100 004 0 0000 0000 0000 000 ? 0.25 1111 1111 1100 ffc ? 25 1110 0111 0000 e70 ? 55 1100 1001 0000 c90 (1) the resolution for the temp adc in internal temperature mode is 0.0625 c/count. table 2 does not list all temperatures. use the following rules to obtain the digital data format for a given temperature or the temperature for a given digital data format. to convert positive temperatures to a digital data format: 1. divide the temperature by the resolution 2. convert the result to binary code with a 12-bit, left-justified format, and msb = 0 to denote a positive sign. example: (50 c) / (0.0625 c / lsb) = 800 = 320h = 0011 0010 0000 to convert a positive digital data format to temperature: 1. convert the 12-bit, left-justified binary temperature result, with the msb = 0 to denote a positive sign, to a decimal number. 2. multiply the decimal number by the resolution to obtain the positive temperature. example: 0011 0010 0000 = 320h = 800 (0.0625 c / lsb) = 50 c to convert negative temperatures to a digital data format: 1. divide the absolute value of the temperature by the resolution, and convert the result to binary code with a 12-bit, left-justified format. 2. generate the twos complement of the result by complementing the binary number and adding one. denote a negative number with msb = 1. example: (| ? 25 c|) / (0.0625 c / lsb) = 400 = 190h = 0001 1001 0000 two's complement format: 1110 0110 1111 + 1 = 1110 0111 0000 to convert a negative digital data format to temperature: 1. generate the twos compliment of the 12-bit, left-justified binary number of the temperature result (with msb = 1, denoting negative temperature result) by complementing the binary number and adding one. this represents the binary number of the absolute value of the temperature. 2. convert to decimal number and multiply by the resolution to get the absolute temperature, then multiply by ? 1 for the negative sign. example: 1110 0111 0000 has twos compliment of 0001 1001 0000 = 0001 1000 1111 + 1 convert to temperature: 0001 1001 0000 = 190h = 400; 400 (0.0625 c / lsb) = 25 c = (| ? 25 c|); (| ? 25 c|) ( ? 1) = ? 25 c 8 submit documentation feedback copyright ? 2007 ? 2015, texas instruments incorporated product folder links: tmp102
tmp102 www.ti.com sbos397f ? august 2007 ? revised december 2015 table 3. 13-bit temperature data format temperature ( c) digital output (binary) hex 150 0 1001 0110 0000 0960 128 0 1000 0000 0000 0800 127.9375 0 0111 1111 1111 07ff 100 0 0110 0100 0000 0640 80 0 0101 0000 0000 0500 75 0 0100 1011 0000 04b0 50 0 0011 0010 0000 0320 25 0 0001 1001 0000 0190 0.25 0 0000 0000 0100 0004 0 0 0000 0000 0000 0000 ? 0.25 1 1111 1111 1100 1ffc ? 25 1 1110 0111 0000 1e70 ? 55 1 1100 1001 0000 1c90 7.3.2 serial interface the tmp102 device operates as a slave device only on the two-wire bus and smbus. connections to the bus are made through the open-drain i/o lines, sda and scl. the sda and scl pins feature integrated spike suppression filters and schmitt triggers to minimize the effects of input spikes and bus noise. the tmp102 device supports the transmission protocol for both fast (1 khz to 400 khz) and high-speed (1 khz to 2.85 mhz) modes. all data bytes are transmitted msb first. 7.3.3 bus overview the device that initiates the transfer is called a master , and the devices controlled by the master are called slaves . the bus must be controlled by a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. to address a specific device, a start condition is initiated, indicated by pulling the data-line (sda) from a high to low logic level when scl is high. all slaves on the bus shift in the slave address byte on the rising edge of the clock, with the last bit indicating whether a read or write operation is intended. during the ninth clock pulse, the slave being addressed responds to the master by generating an acknowledge and by pulling sda pin low. a data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. during the data transfer the sda pin must remain stable when scl is high, because any change in sda pin when scl pin is high is interpreted as a start signal or stop signal. when all data have been transferred, the master generates a stop condition indicated by pulling sda pin from low to high, when the scl pin is high. 7.3.4 serial bus address to communicate with the tmp102, the master must first address slave devices via a slave address byte. the slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or write operation. the tmp102 features an address pin to allow up to four devices to be addressed on a single bus. table 4 describes the pin logic levels used to properly connect up to four devices. copyright ? 2007 ? 2015, texas instruments incorporated submit documentation feedback 9 product folder links: tmp102
tmp102 sbos397f ? august 2007 ? revised december 2015 www.ti.com table 4. address pin and slave addresses device two-wire address a0 pin connection 1001000 ground 1001001 v+ 1001010 sda 1001011 scl 7.3.5 writing and reading operation accessing a particular register on the tmp102 device is accomplished by writing the appropriate value to the pointer register. the value for the pointer register is the first byte transferred after the slave address byte with the r/ w bit low. every write operation to the tmp102 device requires a value for the pointer register (see figure 8 ). when reading from the tmp102 device, the last value stored in the pointer register by a write operation determines which register is read by a read operation. to change the register pointer for a read operation, a new value must be written to the pointer register. this action is accomplished by issuing a slave address byte with the r/ w bit low, followed by the pointer register byte. no additional data are required. the master then generates a start condition and sends the slave address byte with the r/ w bit high to initiate the read command. see figure 7 for details of this sequence. if repeated reads from the same register are desired, continually sending the pointer register bytes is not necessary because the tmp102 remembers the pointer register value until it is changed by the next write operation. register bytes are sent with the most significant byte first, followed by the least significant byte. 7.3.6 slave mode operations the tmp102 can operate as a slave receiver or slave transmitter. as a slave device, the tmp102 never drives the scl line. 7.3.6.1 slave receiver mode the first byte transmitted by the master is the slave address, with the r/ w bit low. the tmp102 then acknowledges reception of a valid address. the next byte transmitted by the master is the pointer register. the tmp102 then acknowledges reception of the pointer register byte. the next byte or bytes are written to the register addressed by the pointer register. the tmp102 acknowledges reception of each data byte. the master can terminate data transfer by generating a start or stop condition.. 7.3.6.2 slave transmitter mode the first byte transmitted by the master is the slave address, with the r/ w bit high. the slave acknowledges reception of a valid slave address. the next byte is transmitted by the slave and is the most significant byte of the register indicated by the pointer register. the master acknowledges reception of the data byte. the next byte transmitted by the slave is the least significant byte. the master acknowledges reception of the data byte. the master terminates data transfer by generating a not-acknowledge on reception of any data byte, or generating a start or stop condition. 7.3.7 smbus alert function the tmp102 device supports the smbus alert function. when the tmp102 device operates in interrupt mode (tm = 1), the alert pin can be connected as an smbus alert signal. when a master senses that an alert condition is present on the alert line, the master sends an smbus alert command (0001 1001) to the bus. if the alert pin is active, the device acknowledges the smbus alert command and responds by returning the slave address on the sda line. the eighth bit (lsb) of the slave address byte indicates if the alert condition was caused by the temperature exceeding t high or falling below t low . for pol = 0, the lsb is low if the temperature is greater than or equal to t high ; this bit is high if the temperature is less than t low . the polarity of this bit is inverted if pol = 1. see figure 10 for details of this sequence. if multiple devices on the bus respond to the smbus alert command, arbitration during the slave address portion of the smbus alert command determines which device clears the alert status. the device with the lowest two- wire address wins the arbitration. if the tmp102 device wins the arbitration, its alert pin inactivates at the completion of the smbus alert command. if the tmp102 device loses the arbitration, its alert pin remains active. 10 submit documentation feedback copyright ? 2007 ? 2015, texas instruments incorporated product folder links: tmp102
tmp102 www.ti.com sbos397f ? august 2007 ? revised december 2015 7.3.8 general call the tmp102 device responds to a two-wire general call address (000 0000) if the eighth bit is 0. the device acknowledges the general call address and responds to commands in the second byte. if the second byte is 0000 0110, the tmp102 device internal registers are reset to power-up values. the tmp102 device does not support the general address acquire command. 7.3.9 high-speed (hs) mode in order for the two-wire bus to operate at frequencies above 400 khz, the master device must issue an hs- mode master code (0000 1xxx) as the first byte after a start condition to switch the bus to high-speed operation. the tmp102 device does not acknowledge this byte, but switches the input filters on sda and scl and the output filters on sda to operate in hs-mode, allowing transfers of up to 2.85 mhz. after the hs-mode master code has been issued, the master transmits a two-wire slave address to initiate a data transfer operation. the bus continues to operate in hs-mode until a stop condition occurs on the bus. upon receiving the stop condition, the tmp102 device switches the input and output filters back to fast-mode operation.. 7.3.10 timeout function the tmp102 device resets the serial interface if scl is held low for 30 ms (typ) between a start and stop condition. the tmp102 device releases the sda line if the scl pin is pulled low and waits for a start condition from the host controller. to avoid activating the time-out function, maintaining a communication speed of at least 1 khz for scl operating frequency is necessary.. 7.3.11 timing diagrams the tmp102 device is two-wire, smbus, and i 2 c-interface compatible. figure 7 , figure 8 , figure 9 , and figure 10 list the various operations on the tmp102 device. parameters for figure 7 are defined in the timing requirements table. the bus definitions are defined as follows: acknowledge each receiving device, when addressed, is obliged to generate an acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge clock pulse. setup and hold times must be taken into account. on a master receive, the termination of the data transfer can be signaled by the master generating a not-acknowledge (1) on the last byte that has been transmitted by the slave. bus idle both sda and scl lines remain high. data transfer the number of data bytes transferred between a start and a stop condition is not limited and is determined by the master device. the tmp102 device can also be used for single byte updates. to update only the ms byte, terminate the communication by issuing a start or stop communication on the bus. start data transfer a change in the state of the sda line, from high to low, when the scl line is high, defines a start condition. each data transfer is initiated with a start condition. stop data transfer a change in the state of the sda line from low to high when the scl line is high defines a stop condition. each data transfer is terminated with a repeated start or stop condition. figure 7. two-wire timing diagram copyright ? 2007 ? 2015, texas instruments incorporated submit documentation feedback 11 product folder links: tmp102 scl sda t (low) t rc t fc t (hdsta) t (hdsta) t (hddat) t (sudat) t (high) t (susta) t (susto) t (buf) s s p p t rd t fd
tmp102 sbos397f ? august 2007 ? revised december 2015 www.ti.com figure 8. two-wire timing diagram for write word format figure 9. two-wire timing diagram for read word format 12 submit documentation feedback copyright ? 2007 ? 2015, texas instruments incorporated product folder links: tmp102 frame 1 two-wire slave address byte frame 2 pointer register byte 1 start by master ack by device ack by device frame 3 two-wire slave address byte frame 4 data byte 1 read register start by master ack by device ack by master (2) from device 1 9 1 9 1 9 1 9 sda scl 0 0 1 r/w 0 0 0 0 0 0 p1 p0 ? ? ? sda (continued) scl (continued) sda (continued) scl (continued) 1 0 0 1 0 a1 (1) a0 (1) 0 a1 (1) a0 (1) r/w d7 d6 d5 d4 d3 d2 d1 d0 frame 5 data byte 2 read register stop by master ack by master (3) from device 1 9 d7 d6 d5 d4 d3 d2 d1 d0 stop by master note: (1) the value of a0 and a1 are determined by the add0 pin. (2) master should leave sda high to terminate a single-byte read operation.(3) master should leave sda high to terminate a two-byte read operation. frame 1 two-wire slave address byte frame 2 pointer register byte frame 4 data byte 2 1 start by master ack by device ack by device ack by device stop by master 1 9 1 1 d7 d6 d5 d4 d3 d2 d1 d0 9 frame 3 data byte 1 ack by device 1 d7 sda (continued) scl (continued) d6 d5 d4 d3 d2 d1 d0 9 9 sda scl 0 0 1 0 a1 (1) a0 (1) r/w 0 0 0 0 0 0 p1 p0 ? ? note: (1) the value of a0 and a1 are determined by the add0 pin.
tmp102 www.ti.com sbos397f ? august 2007 ? revised december 2015 figure 10. timing diagram for smbus alert 7.4 device functional modes 7.4.1 continuos-conversion mode the default mode of the tmp102 device is continuos conversion mode. during continuos-conversion mode, the adc performs continuos temperature conversions and stores each results to the temperature register, overwriting the result from the previous conversion. the conversion rate bits, cr1 and cr0, configure the tmp102 device for conversion rates of 0.25 hz, 1 hz, 4 hz, or 8 hz. the default rate is 4 hz. the tmp102 device has a typical conversion time of 26 ms. to achieve different conversion rates, the tmp102 device makes a conversion and then powers down to wait for the appropriate delay set by cr1 and cr0. table 5 lists the settings for cr1 and cr0. table 5. conversion rate settings cr1 cr0 conversion rate 0 0 0.25 hz 0 1 1 hz 1 0 4 hz (default) 1 1 8 hz after power-up or general-call reset, the tmp102 immediately starts a conversion, as shown in figure 11 . the first result is available after 26 ms (typical). the active quiescent current during conversion is 40 a (typical at +27 c). the quiescent current during delay is 2.2 a (typical at +27 c). (1) delay is set by cr1 and cr0. figure 11. conversion start 7.4.2 extended mode (em) the extended-mode bit configures the device for normal mode operation (em = 0) or extended mode operation (em = 1). in normal mode, the temperature register and high- and low-limit registers use a 12-bit data format. normal mode is used to make the tmp102 device compatible with the tmp75 device. extended mode (em = 1) allows measurement of temperatures above 128 c by configuring the temperature register, and high- and low-limit registers for 13-bit data format. copyright ? 2007 ? 2015, texas instruments incorporated submit documentation feedback 13 product folder links: tmp102 startup start of conversion delay (1) 26ms 26ms note: (1) the value of a0 and a1 are determined by the add0 pin. frame 1 smbus alert response address byte frame 2 slave address from device start by master ack by device from device nack by master stop by master 1 9 1 9 sda scl alert 0 0 0 1 1 0 0 r/w 1 0 0 1 a1 a0 status
tmp102 sbos397f ? august 2007 ? revised december 2015 www.ti.com 7.4.3 shutdown mode (sd) the shutdown-mode bit saves maximum power by shutting down all device circuitry other than the serial interface, reducing current consumption to typically less than 0.5 a. shutdown mode enables when the sd bit is 1; the device shuts down when current conversion is completed. when sd is equal to 0, the device maintains a continuous conversion state. 7.4.4 one-shot/conversion ready (os) the tmp102 device features a one-shot temperature measurement mode. when the device is in shutdown mode, writing a 1 to the os bit starts a single temperature conversion. during the conversion, the os bit reads '0'. the device returns to the shutdown state at the completion of the single conversion. after the conversion, the os bit reads 1. this feature reduces power consumption in the tmp102 device when continuous temperature monitoring is not required. as a result of the short conversion time, the tmp102 device achieves a higher conversion rate. a single conversion typically takes 26 ms and a read can take place in less than 20 s. when using one-shot mode, 30 or more conversions per second are possible. 7.4.5 thermostat mode (tm) the thermostat-mode bit indicates to the device whether to operate in comparator mode (tm = 0) or interrupt mode (tm = 1). 7.4.5.1 comparator mode (tm = 0) in comparator mode (tm = 0), the alert pin is activated when the temperature equals or exceeds the value in the t (high) register and remains active until the temperature falls below the value in the t (low) register. for more information on the comparator mode, see the high- and low-limit registers section. 7.4.5.2 interrupt mode (tm = 1) in interrupt mode (tm = 1), the alert pin is activated when the temperature exceeds t (high) or goes below t (low) registers. the alert pin is cleared when the host controller reads the temperature register. for more information on the interrupt mode, see the high- and low-limit registers section. 7.5 programming 7.5.1 pointer register figure 12 illustrates the internal register structure of the tmp102 device. the 8-bit pointer register of the device is used to address a given data register. the pointer register uses the two least-significant bytes (lsbs) (see table 15 and table 16 ) to identify which of the data registers must respond to a read or write command. table 6 identifies the bits of the pointer register byte. during a write command, p2 through p7 must always be '0'. table 7 describes the pointer address of the registers available in the tmp102 device. the power-up reset value of p1 and p0 is 00. by default, the tmp102 device reads the temperature on power up. 14 submit documentation feedback copyright ? 2007 ? 2015, texas instruments incorporated product folder links: tmp102
tmp102 www.ti.com sbos397f ? august 2007 ? revised december 2015 programming (continued) figure 12. internal register structure table 6. pointer register byte p7 p6 p5 p4 p3 p2 p1 p0 0 0 0 0 0 0 register bits table 7. pointer addresses p1 p0 register 0 0 temperature register (read only) 0 1 configuration register (read/write) 1 0 t low register (read/write) 1 1 t high register (read/write) 7.5.2 temperature register the temperature register of the tmp102 is configured as a 12-bit, read-only register (configuration register em bit = 0, see the extended mode section), or as a 13-bit, read-only register (configuration register em bit = 1) that stores the output of the most recent conversion. two bytes must be read to obtain data, and are described in table 8 and table 9 . note that byte 1 is the most significant byte, followed by byte 2, the least significant byte. the first 12 bits (13 bits in extended mode) are used to indicate temperature. the least significant byte does not have to be read if that information is not needed. table 8. byte 1 of temperature register (1) d7 d6 d5 d4 d3 d2 d1 d0 t11 t10 t9 t8 t7 t6 t5 t4 (t12) (t11) (t10) (t9) (t8) (t7) (t6) (t5) (1) extended mode 13-bit configuration shown in parenthesis. copyright ? 2007 ? 2015, texas instruments incorporated submit documentation feedback 15 product folder links: tmp102 i/o control interface sclsda temperature register configuration register t low register t high register pointer register
tmp102 sbos397f ? august 2007 ? revised december 2015 www.ti.com table 9. byte 2 of temperature register (1) d7 d6 d5 d4 d3 d2 d1 d0 t3 t2 t1 t0 0 0 0 0 (t4) (t3) (t2) (t1) (t0) (0) (0) (1) (1) extended mode 13-bit configuration shown in parenthesis. 7.5.3 configuration register the configuration register is a 16-bit read/write register used to store bits that control the operational modes of the temperature sensor. read/write operations are performed msb first. table 10 and table 11 list the format and the power-up or reset value of the configuration register. for compatibility, table 10 and table 11 correspond to the configuration register in the tmp75 device and tmp275 device (for more information see the device data sheets, sbos288 and sbos363 , respectively). all registers are updated byte by byte. table 10. byte 1 of configuration and power-up or reset format d7 d6 d5 d4 d3 d2 d1 d0 os r1 r0 f1 f0 pol tm sd 0 1 1 0 0 0 0 0 table 11. byte 2 of configuration and power-up or reset format d7 d6 d5 d4 d3 d2 d1 d0 cr1 cr0 al em 0 0 0 0 1 0 1 0 0 0 0 0 7.5.3.1 shutdown mode (sd) the shutdown-mode bit saves maximum power by shutting down all device circuitry other than the serial interface, reducing current consumption to typically less than 0.5 a. shutdown mode enables when the sd bit is 1; the device shuts down when current conversion is completed. when sd is equal to 0, the device maintains a continuous conversion state 7.5.3.2 thermostat mode (tm) the thermostat mode bit indicates to the device whether to operate in comparator mode (tm = 0) or interrupt mode (tm = 1). for more information on comparator and interrupt modes, see the high- and low-limit registers section. 7.5.3.3 polarity (pol) the polarity bit allows the user to adjust the polarity of the alert pin output. if the pol bit is set to 0 (default), the alert pin becomes active low. when the pol bit is set to 1, the alert pin becomes active high and the state of the alert pin is inverted. the operation of the alert pin in various modes is illustrated in figure 13 . 16 submit documentation feedback copyright ? 2007 ? 2015, texas instruments incorporated product folder links: tmp102
tmp102 www.ti.com sbos397f ? august 2007 ? revised december 2015 figure 13. output transfer function diagrams 7.5.3.4 fault queue (f1/f0) a fault condition exists when the measured temperature exceeds the user-defined limits set in the t high and t low registers. additionally, the number of fault conditions required to generate an alert may be programmed using the fault queue. the fault queue is provided to prevent a false alert as a result of environmental noise. the fault queue requires consecutive fault measurements in order to trigger the alert function. table 12 defines the number of measured faults that may be programmed to trigger an alert condition in the device. for t high and t low register format and byte order, see the high- and low-limit registers section. table 12. tmp102 fault settings f1 f0 consecutive faults 0 0 1 0 1 2 1 0 4 1 1 6 7.5.3.5 converter resolution (r1/r0) the converter resolution bits, r1 and r0, are read-only bits. the tmp102 converter resolution is set at device start-up to 11 which sets the temperature register to a 12 bit-resolution. 7.5.3.6 one-shot (os) when the device is in shutdown mode, writing a 1 to the os bit starts a single temperature conversion. during the conversion, the os bit reads '0'. the device returns to the shutdown state at the completion of the single conversion. for more information on the one-shot conversion mode, see the one-shot/conversion ready (os) section. 7.5.3.7 em bit the extended-mode bit configures the device for normal mode operation (em = 0) or extended mode operation (em = 1). in normal mode, the temperature register, high-limit register, and low-limit register use a 12-bit data format. for more information on the extended mode, see the extended mode (em) section. copyright ? 2007 ? 2015, texas instruments incorporated submit documentation feedback 17 product folder links: tmp102 measured temperature t high t low device alert pin (comparator mode) pol = 0 device alert pin (interrupt mode) pol = 0 device alert pin (comparator mode) pol = 1 device alert pin (interrupt mode) pol = 1 read read time read
tmp102 sbos397f ? august 2007 ? revised december 2015 www.ti.com 7.5.3.8 alert (al bit) the al bit is a read-only function. reading the al bit provides information about the comparator mode status. the state of the pol bit inverts the polarity of data returned from the al bit. when the pol bit equals 0, the al bit reads as 1 until the temperature equals or exceeds t (high) for the programmed number of consecutive faults, causing the al bit to read as 0. the al bit continues to read as 0 until the temperature falls below t (low) for the programmed number of consecutive faults, when it again reads as 1. the status of the tm bit does not affect the status of the al bit.. 7.5.3.9 conversion rate (cr) the conversion rate bits, cr1 and cr0, configure the tmp102 device for conversion rates of 0.25 hz, 1 hz, 4 hz, or 8 hz. the default rate is 4 hz. for more information on the conversion rate bits, see table 5 . 7.5.4 high- and low-limit registers the temperature limits are stored in the t (low) and t (high) registers in the same format as the temperature result, and their values are compared to the temperature result on every conversion. the outcome of the comparison drives the behavior of the alert pin, which operates as a comparator output or an interrupt, and is set by the tm bit in the configuration register. in comparator mode (tm = 0), the alert pin becomes active when the temperature equals or exceeds the value in t high and generates a consecutive number of faults according to fault bits f1 and f0. the alert pin remains active until the temperature falls below the indicated t low value for the same number of faults. in interrupt mode (tm = 1), the alert pin becomes active when the temperature equals or exceeds the value in t high for a consecutive number of fault conditions (as shown in table 5 ). the alert pin remains active until a read operation of any register occurs, or the device successfully responds to the smbus alert response address. the alert pin will also be cleared if the device is placed in shutdown mode. when the alert pin is cleared, it becomes active again only when temperature falls below t low , and remains active until cleared by a read operation of any register or a successful response to the smbus alert response address. when the alert pin is cleared, the above cycle repeats, with the alert pin becoming active when the temperature equals or exceeds t high . the alert pin can also be cleared by resetting the device with the general call reset command. this action also clears the state of the internal registers in the device, returning the device to comparator mode (tm = 0). both operational modes are represented in figure 13 . table 13 through table 16 describe the format for the t high and t low registers. note that the most significant byte is sent first, followed by the least significant byte. power-up reset values for t high and t low are: t high = +80 c and t low = +75 c. the format of the data for t high and t low is the same as for the temperature register. table 13. byte 1 temperature register high (1) d7 d6 d5 d4 d3 d2 d1 d0 h11 h10 h9 h8 h7 h6 h5 h4 (h12) (h11) (h10) (h9) (h8) (h7) (h6) (h5) (1) extended mode 13-bit configuration shown in parenthesis. table 14. byte 2 temperature register high d7 d6 d5 d4 d3 d2 d1 d0 h3 h2 h1 h0 0 0 0 0 (h4) (h3) (h2) (h1) (h0) (0) (0) (0) table 15. byte 1 temperature register low (1) d7 d6 d5 d4 d3 d2 d1 d0 l11 l10 l9 l8 l7 l6 l5 l4 (l12) (l11) (l10) (l9) (l8) (l7) (l6) (l5) (1) extended mode 13-bit configuration shown in parenthesis. 18 submit documentation feedback copyright ? 2007 ? 2015, texas instruments incorporated product folder links: tmp102
tmp102 www.ti.com sbos397f ? august 2007 ? revised december 2015 table 16. byte 2 temperature register low d7 d6 d5 d4 d3 d2 d1 d0 l3 l2 l1 l0 0 0 0 0 (l4) (l3) (l2) (l1) (l0) (0) (0) (0) copyright ? 2007 ? 2015, texas instruments incorporated submit documentation feedback 19 product folder links: tmp102
tmp102 sbos397f ? august 2007 ? revised december 2015 www.ti.com 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the tmp102 device is used to measure the pcb temperature of the board location where the device is mounted. the programmable address options allow up to four locations on the board to be monitored on a single serial bus. 8.2 typical application figure 14. typical connections 8.2.1 design requirements the tmp102 device requires pullup resistors on the scl, sda, and alert pins. the recommended value for the pullup resistors is 5-k . in some applications the pullup resistor can be lower or higher than 5 k but must not exceed 3 ma of current on any of those pins. a 0.01- f bypass capacitor on the supply is recommended as shown in figure 14 . the scl and sda lines can be pulled up to a supply that is equal to or higher than v+ through the pullup resistors. to configure one of four different addresses on the bus, connect the add0 pin to either the gnd, v+, sda, or scl pin. 8.2.2 detailed design procedure place the tmp102 device in close proximity to the heat source that must be monitored, with a proper layout for good thermal coupling. this placement ensures that temperature changes are captured within the shortest possible time interval. to maintain accuracy in applications that require air or surface temperature measurement, care must be taken to isolate the package and leads from ambient air temperature. a thermally-conductive adhesive is helpful in achieving accurate surface temperature measurement. 20 submit documentation feedback copyright ? 2007 ? 2015, texas instruments incorporated product folder links: tmp102 scl gnd alert 2 4 1 add0 v+ 6 3 5 0.01 f two-wire host controller tmp102 1.4 v to 3.6 v sda pullup resistors supply bypass capacitor supply voltage 5 k
tmp102 www.ti.com sbos397f ? august 2007 ? revised december 2015 typical application (continued) the tmp102 device is a very low-power device and generates very low noise on the supply bus. applying an rc filter to the v+ pin of the tmp102 device can further reduce any noise that the tmp102 device might propagate to other components. r (f) in figure 15 must be less than 5 k ? and c (f) must be greater than 10 nf. figure 15. noise reduction techniques 8.2.3 application curve figure 16 shows the step response of the tmp102 device to a submersion in an oil bath of 100 o c from room temperature (27 o c). the time-constant, or the time for the output to reach 63% of the input step, is 0.8 s. the time-constant result depends on the printed circuit board (pcb) that the tmp102 device is mounted. for this test, the tmp102 device was soldered to a two-layer pcb that measured 0.375 inch 0.437 inch. space figure 16. temperature step response copyright ? 2007 ? 2015, texas instruments incorporated submit documentation feedback 21 product folder links: tmp102 time (s) temperature ( q c) -1 1 3 5 7 9 11 13 15 17 19 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 device scl sda gnd v+ alert add0 c (f) 10 nf r (f) 5 k supply voltage
tmp102 sbos397f ? august 2007 ? revised december 2015 www.ti.com 9 power supply recommendations the tmp102 device operates with power supply in the range of 1.4 to 3.6 v. the device is optimized for operation at 3.3-v supply but can measure temperature accurately in the full supply range. a power-supply bypass capacitor is required for proper operation. place this capacitor as close as possible to the supply and ground pins of the device. a typical value for this supply bypass capacitor is 0.01 f. applications with noisy or high-impedance power supplies may require additional decoupling capacitors to reject power-supply noise. 10 layout 10.1 layout guidelines place the power-supply bypass capacitor as close as possible to the supply and ground pins. the recommended value of this bypass capacitor is 0.01 f. additional decoupling capacitance can be added to compensate for noisy or high-impedance power supplies. pull up the open-drain output pins (sda , scl and alert) through 5- k pullup resistors. 10.2 layout example figure 17. tmp102 layout example 22 submit documentation feedback copyright ? 2007 ? 2015, texas instruments incorporated product folder links: tmp102 serial bus traces pullup resistors supply bypass capacitor via to power or ground plane via to internal layer supply voltage scl gnd alert add0 v+ sda ground plane for thermal coupling to heat source heat source
tmp102 www.ti.com sbos397f ? august 2007 ? revised december 2015 11 device and documentation support 11.1 documentation support 11.1.1 related documentation for related documentation see the following: ? tmp175, tmp75 data sheet, sbos288 ? tmp275 data sheet, sbos363 ? capacitive touch operated automotive led dome light with haptics feedback design guide 11.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.3 trademarks e2e is a trademark of texas instruments. smbus is a trademark of intel, inc. all other trademarks are the property of their respective owners. 11.4 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. copyright ? 2007 ? 2015, texas instruments incorporated submit documentation feedback 23 product folder links: tmp102
package option addendum www.ti.com 4-may-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples hpa00330aidrlr active sot-5x3 drl 6 4000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 cbz hpa00330aidrlrg4 active sot-5x3 drl 6 4000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 cbz tmp102aidrlr active sot-5x3 drl 6 4000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 cbz tmp102aidrlrg4 active sot-5x3 drl 6 4000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 cbz tmp102aidrlt active sot-5x3 drl 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 cbz TMP102AIDRLTG4 active sot-5x3 drl 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 cbz (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device.
package option addendum www.ti.com 4-may-2017 addendum-page 2 (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of tmp102 : ? automotive: tmp102-q1 note: qualified version definitions: ? automotive - q100 devices qualified for high-reliability automotive applications targeting zero defects
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tmp102aidrlr sot-5x3 drl 6 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 q3 package materials information www.ti.com 4-may-2017 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) tmp102aidrlr sot-5x3 drl 6 4000 202.0 201.0 28.0 package materials information www.ti.com 4-may-2017 pack materials-page 2

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own risk. designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. designer will fully indemnify ti and its representatives against any damages, costs, losses, and/or liabilities arising out of designer ? s non- compliance with the terms and provisions of this notice. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2017, texas instruments incorporated

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